skew controlled sdram buffe r W191 rev 1.0, november 20, 2006 page 1 of 9 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax:(408) 855-0550 www.spectralinear.com features ? six skew controlled cmos outputs output skew between any two outputs is less than 150 ps smbus serial configuration interface 2.5 ns to 5 ns propagation delay dc to 133 mhz operation (commercial) dc to 100 mhz operation (industrial) single 3.3v supply voltage low power cmos design packaged in a 16-pin ssop (small shrink outline package) key specifications supply voltages: ...................................... v ddq3 = 3.3v 5% operating temperature: (commercial) ............. 0c to +70c operating temperature: (industrial) .............. ?40c to +85c input threshold:...................................................1.5v typical maximum input voltage: .................................. v ddq3 + 0.5v input frequency: (commercial) ................ ........0 to 133 mhz input frequency: (industrial) .............................0 to 100 mhz buf_in to sdram0:5 propagation delay:.......2.5 ns to 5 ns min. output edge rate: ............................................. 1.0v/ns max. output skew: ..................................................... 150 ps output duty cycle:...................................45/55% worst case output impedance: ...................................................15 : typ. block diagram pin configuration [1] sdram0 sdram1 sdram2 sdram3 sdram4 sdram5 smbus sclock sdata device control buf_in vddq3 sdram5 gnd sdram4 vddq3 sdram3 gnd sclk 16 15 14 13 12 11 10 9 sdram0 gnd sdram1 buf_in gnd sdram2 vddq3 sdata 1 2 3 4 5 6 7 8 note: 1. internal pull-up resistor of 250k on sdata and sclk.
W191 rev 1.0, november 20, 2006 page 2 of 9 overview the W191 is a skew controlled fanout buffer optimized for interface with registered dimms. functional description output drivers the W191 output buffers are cmos type which deliver a rail-to-rail (gnd to vdd) output voltage swing into a nominal capacitive load. thus, output signaling is both ttl and cmos level compatible. nominal output buffer impedance is 15 : . serial control serial control data is written to the W191 in ten bytes of eight bits each. bytes are written in the order shown in table 1 writing data bytes each bit in the data bytes control a particular device function. bits are written msb (most significant bit) first, which is bit 7. table 1 gives the bit formats for registers located in data bytes 0-2. pin definitions pin name pin no. pin type pin description sdram0:5 1, 3, 6, 11, 13, 15 o sdram outputs: provides buffered copy of buf_in. the propagation delay from a rising input edge to a rising output edge is 2.5 to 5 ns. all outputs are skew controlled to within 150 ps of each other. buf_in 4 i clock input: this clock input has an input threshold vo ltage of 1.5v (typ). sdata 8 i/o smbus data input: data should be presented to this input as described in the smbus section of this data sheet. internal 250-k : pull-up resistor. sclock 9 i smbus clock input: the smbus data clock should be presented to this input as described in the smbus section of this data sheet. internal 250-k : pull-up resistor. vddq3 7, 12, 16 p power connection: power supply for core logic and output buffers. connected to 3.3v supply. gnd 2, 5, 10, 14 g ground connection: connect all ground pins to the common system ground plane. table 1. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the W191 to accept the bits in data bytes 0-6 for internal register configuration. since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the W191 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don?t care unused by the W191, therefore bit values are ignored (don?t care). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 byte count don?t care unused by the W191, therefore bit values are ignored (don?t care). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communi- cation protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 refer to table 2 the data bits in these bytes set internal W191 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to ta ble 2 . 5 data byte 1 6 data byte 2 7 data byte 3 don?t care 8 data byte 4 9 data byte 5 10 data byte 6
W191 rev 1.0, november 20, 2006 page 3 of 9 table 2. data bytes 0?2 serial configuration map [2] bit(s) affected pin control function bit control pin no. pin name 0 1 data byte 0 sdram active/inactive register (1 = enable, 0 = disable) 7 6 sdram2 clock output disable low active 6 -- -- (reserved) -- -- 5 -- -- (reserved) -- -- 4 -- -- (reserved) -- -- 3 -- -- (reserved) -- -- 2 3 sdram1 clock output disable low active 1 -- -- (reserved) -- -- 0 1 sdram0 clock output disable -- -- data byte 1 sdram active/inactive register (1 = enable, 0 = disable) 7 -- -- clock output disable -- -- 6 15 sdram5 clock output disable low active 5 -- -- clock output disable -- -- 4 -- -- (reserved) -- -- 3 13 sdram4 clock output disable low active 2 -- -- (reserved) -- -- 1 -- -- (reserved) -- -- 0 -- -- (reserved) -- -- data byte 2 sdram active/inactive register (1 = enable, 0 = disable) 7 11 sdram3 clock output disable low active 6 -- -- (reserved) -- -- 5 -- -- (reserved) -- -- 4 -- -- (reserved) -- -- 3 -- -- (reserved) -- -- 2 -- -- (reserved) -- -- 1 -- -- (reserved) -- -- 0 -- -- (reserved) -- -- note: 2. at power up all sdram outputs are enabled and active. program reserved bits to 0.
W191 rev 1.0, november 20, 2006 page 4 of 9 absolute maximum ratings [3] stresses greater than those listed in this table may cause permanent damage to the device. these represent a stress rating only. operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. dc electrical characteristics: t a = 0c to +70c (commercial), v ddq3 = 3.3v 5%,t a = ?40c to +85c (industrial), v ddq3 = 3.3v 5% [4] parameter description rating unit v ddq3 , v in voltage on any pin with respect to gnd ?0.5 to + 7.0 v t stg storage temperature ?65 to + 150 c t b ambient temperature under bias ?55 to + 125 c t a operating temperature (commercial) 0 to + 70 c t a operating temperature (industrial) ?40 to + 85 c parame- ter description test condition min. typ. max. unit i dd 3.3v supply current buf_in = 100 mhz 173 ma i dd 3.3v supply current in three-state buf_in = 100 mhz 5 ma logic inputs (buf_in, oe, sclock, sdata) v il input low voltage gnd?0.3 0.8 v v ih input high voltage 2.0 v ddq3 +0.5 v i ileak input leakage current, buf_in ?5 +5 a i ileak input leakage current [5] ?20 +5 a logic outputs (sdram0:5) v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 3.1 v i ol output low current v ol = 1.5v 65 100 160 ma i oh output high current v oh = 1.5v 70 110 185 ma pin capacitance/inductance c in input pin capacitance (except buf_in) 5 pf c out output pin capacitance 6 pf l in input pin inductance 7nh notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 4. outputs loaded by 6? 60 : transmission lines with 20 pf capacitors. 5. oe, sclock, and sdata logic pins have a 250-k : internal pull-up resistor (not cmos level).
W191 rev 1.0, november 20, 2006 page 5 of 9 ac electrical characteristics: t a = 0c to +70c (commercial), v ddq3 = 3.3v 5%,t a = -40c to +85c (industrial), v ddq3 = 3.3v 5% (lump capacitance test load = 30pf) parameter description test condition min. typ. max. unit f in input frequency (commercial) 0 133 mhz f in input frequency (industrial) 0 100 mhz t r output rise edge rate measured from 0.4v to 2.4v 1.0 4.0 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1.0 4.0 v/ns t sr output skew, rising edges 150 ps t sf output skew, falling edges 150 ps t en output enable time 1.0 8.0 ns t dis output disable time 1.0 8.0 ns t pr rising edge propagation delay 2.5 5.0 ns t pf falling edge propagation delay 2.5 5.0 ns t d duty cycle measured at 1.5v 45 55 % z o ac output impedance 15 :
W191 rev 1.0, november 20, 2006 page 6 of 9 how to use the serial data interface electrical requirements figure 1 illustrates electrical characteristics for the serial interface bus used with the W191. devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. the pull-up resistor on the bus (both clock and data lines) establish a default logic 1. all bus devices generally have logic inputs to receive data. although the W191 is a receive-only device (no data write-back capability), it does transmit an ?acknowledge? data pulse after each byte is received. thus, the sdata line can both transmit and receive data. the pull-up resistor should be sized to meet the rise and fall times specified in ac parameters, taking into consideration total bus line capacitance. signaling requirements as shown in figure 2 , valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. a transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). a write sequence is initiated by a ?start bit? as shown in figure 3 . a ?stop bit? signifies that a transmission has ended. as stated previously, the W191 sends an ?acknowledge? pulse after receiving eight data bits in each byte as shown in figure 4 . sending data to the W191 the device accepts data once it has detected a valid start bit and address byte sequence. device functionality is changed upon the receipt of each data bit (registers are not double buffered). partial transmission is allowed meaning that a trans- mission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). trans- mission is truncated with either a stop bit or new start bit (restart condition). . figure 1. serial interface bus electrical characteristics data in data out n clock in clock out chip set (serial bus master transmitter) sdclk sdata serial bus clock line serial bus data line n data in data out clock in clock device (serial bus slave receiver) sclock sdata n ~ 2k : ~ 2k : vdd vdd
W191 rev 1.0, november 20, 2006 page 7 of 9 figure 2. serial data bus valid data bit figure 3. serial data bus start and stop bit t a c k valid data bit change of data allowed a k start bit stop bit
W191 rev 1.0, november 20, 2006 page 8 of 9 msb 12345678a12345678a 1234 sclock 12345678a 11 01 001 0 lsb msb msb lsb sdata sdata signaling from system core logic start condition msb lsb slave address (first byte) command code (second byte) last data byte (last byte) byte count (third byte) stop condition signaling by clock device acknowledgment bit from clock device figure 4. serial data bus write sequence t sthd t low t r t high t f t dsu t dhd t sp t spsu t sthd t spsu t spf sdata sclock figure 5. serial data bus timing diagrams ordering information ordering code package type temperature range W191hi 16 pin = ssop (150 mil) i = industrial W191h 16 pin = ssop (150 mil) commercial
rev 1.0, november 20, 2006 page 9 of 9 W191 while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear inc., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package diagrams shrink small outline package (ssop 150 inch)
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